The invention relates to semiconductor fabrication, and more particularly to a technique for increasing Ion/Ioff ratios in FinFETs, nano-wires, and other similar structures.
As integrated circuit technologies continue to push into higher densities, a number of transistor types have become popular which involve one or more narrow channel structures wrapped with a gate electrode. The channel structures are often called fins, and transistors that include them are sometimes called FinFETs, described for example in D. Hisamoto et al., IEDM, 1998; and N. Lindert et al., IEEE Electron Device Letters, p. 487, 2001, both incorporated by reference herein for their teachings. The fins comprise semiconductor bodies usually arranged in parallel on the substrate, so that they project vertically upwards from the substrate. A gate dielectric layer overlies the sides and top of the fins, and a gate conductor, which can be implemented using metal or polysilicon for example, extends across the fins and over the gate dielectric layer. On either side of the gate conductor, source and drain regions are implemented in the fins. The FET transistors that result have source, channel and drain regions in the fins, and a gate overlying the fins. Such transistors are often called multi-gate transistors, because the gate conductor wraps around three sides of the fins, and as a result increases the effective width of the channel. In a future proposed structure the gate wraps entirely around the channel structure, in which case the multi-gate transistor is sometimes called a nano-wire. As used herein, however, nano-wires are considered a special case of FinFETs and the channel structures are still sometimes referred to herein as fins.
The fins used to implement the FinFET transistors can be quite narrow. As a result of the multi-gate gate structure and the narrow widths of the fins, FinFET transistors have excellent performance characteristics and small layout areas. But even with such narrow fins, the electric field generated by the gate control voltage when the device is in its off state can be limited in depth and may not extend sufficiently into the cross-sectional middle of the fin. This causes leakage through the middle of the fin. The wider the fin, the higher the leakage because the middle is too far from the gate to be under gate voltage control. Thus the Ion/Ioff ratio suffers. Manufacturers can reduce this problem by narrowing the fin further, but this solution is difficult to implement because the mechanical instability and line edge roughness of such a narrow fin can cause yield loss.
Accordingly, there is a need for better ways to improve the Ion/Ioff ratio in multi-gate transistors.